1. Field of the Invention
The present invention generally relates to a chip-on-glass (COG) structure liquid crystal display (LCD) having a chip mounted on a glass substrate, and more particularly, to a COG structure liquid crystal display having a wiring structure which reduces the pixel peripheral area of a liquid crystal display panel.
2. Description of the Related Art
Conventional COG structure liquid crystal displays are well known and include a chip for driving a liquid crystal display panel which is mounted on a glass substrate constituting the liquid crystal display panel. FIG. 4 illustrates an exemplary method of connecting the chips of the conventional COG structure liquid crystal display to a flexible printed circuit (FPC).
In FIG. 4, a plurality of chips 53 are aligned on a glass substrate 51 and on an outer end of a color filter 52 constituting a liquid crystal display portion of the liquid crystal display panel. A plurality of thin film transistor (TFT) connect pins 54-1, for driving the TFT constituting the LCD panel, are located on each chip 53 on the side facing the color filter 52. A plurality of FPC connect pins 54-2 are located on each chip 53 on the side facing the end of the glass substrate 51. The TFT connect pins 54-1 are connected to the TFT of the liquid crystal display panel through wires 56 (e.g., for ease of understanding only the wires on both the ends are shown in FIG. 4). The FPC connect pins 54-2 are connected to a flexible printed circuit (FPC) 58 through a connection terminal 57.
The conventional COG structure liquid crystal display described above can provide a liquid crystal panel with reduced thickness. However, the COG structure LCD is problematic, compared to the LCD for which a Tape Automated Bonding (TAB) method is utilized, in that it has difficulty reducing the pixel peripheral area in order to increase the area of the display portion of the LCD panel. That is, in the structure shown in FIG. 4, the chip 53 is connected to the FPC 58 through the FPC connection terminal 57. Thus, a region where the FPC connection terminal 57 is provided is not practical for reducing the pixel peripheral area.
Alternatively, a wiring structure is proposed in Japanese Patent Publication No. 5-107551 as a technique for reducing the pixel peripheral area of the COG structure liquid crystal display. In this structure, the chips are covered with the FPC and the chips are connected to the FPC by a connection terminal situated between the chips.
However, while this wiring structure reduces the pixel peripheral area, it is unsuitable for reducing panel thickness because the chips are covered with the FPC. Thus, the FPC has a wavy structure along the thickness of the panel.
Further, this wiring structure has a problem regarding connection reliability, since all the chips are connected directly to the FPC, similar to the above-mentioned conventional structure, thereby requiring a large number of connectors.
Further, with this structure, it is difficult to reduce size, because the FPC connection terminal is placed between all the chips. Thus, a gap between the chips is always required.
In view of the foregoing and other problems, disadvantages, and drawbacks of the conventional display panels the present invention has been devised, and it is an object of the present invention to provide a COG structure liquid crystal display which solves the above problems and can effectively reduce the pixel peripheral area even in the COG structure.
In a first aspect, a COG structure liquid crystal display according to the present invention includes a chip mounted on a glass substrate. In this COG structure LCD, a common wiring for connecting a plurality of chips to a FPC is formed on the glass substrate. The common wiring is connected to the FPC at at least one position on the common wiring. In the present invention, the common wiring may be connected to FPC connector pins of the chip through pin pads.
Further, in the present invention, the chips are connected to the FPC by the following structure in order to connect the chips to an external device. That is, the common wiring for a plurality of chips is formed on a glass substrate, and the FPC is connected to the common wiring at one or more positions. Thus, there is no need for the FPC connect pad which has been used conventionally on the end of the glass substrate. Consequently, a pixel peripheral area can be reduced in that the FPC connect pad is eliminated. Moreover, the chip is connected to the FPC at at least one position. Thus, the number of connectors can be reduced, and therefore the reliability of the connection can be improved.
The present disclosure relates to subject matter contained in Japanese Patent Application 11-036878, filed Feb. 16, 1999, which is expressly incorporated herein by reference in its entirety.